By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complex strategies and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the full ASIC layout circulation method unique for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time software of Synopsys instruments, used to wrestle a variety of difficulties obvious at VDSM geometries. Readers might be uncovered to an efficient layout technique for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties similar to every part of the layout movement are pointed out, with recommendations and work-around defined intimately. additionally, the most important concerns similar to format, including clock tree synthesis and back-end integration (links to format) also are mentioned at size. additionally, the ebook comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, specific in the direction of optimum synthesis answer.
aim audiences for this booklet are practising ASIC layout engineers and masters point scholars venture complex VLSI classes on ASIC chip layout and DFT ideas.
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Additional info for Advanced ASIC Chip Synthesis Using Synopsys Tools
Figure 1-4 illustrates this approach in a very generic form. PhyC can be used in two modes: RTL-to-placed-gates (rtl2pg) or Gates-to-placed-gates (g2pg). For the former mode, the input to PhyC is the RTL, the floorplan information, along with the necessary setup to include logical and physical libraries. 0 format. The second mode of g2pg is provided that can be used for optimizing an existing gate level netlist based on the floorplan information. In this case, instead of the RTL, the input to PhyC is the gate level netlist.
The clock tree insertion modifies the existing structure of the design. In other words, the netlist in the layout tool is different from the original netlist present in DC. This is because of the fact that the design present in the layout tool contains the clock tree, 32 Chapter 2 whereas the original design in DC does not contain this information. Therefore, the clock tree information should somehow be transferred to the design residing in DC or PT. The new netlist (containing the clock tree information) should be formally verified against the original netlist to ensure that the transfer of clock tree did not break the functionality of the original logic.
7. Insert clock tree in the design using the layout tool. 8. Formal verification between clock tree inserted netlist and the original scan inserted netlist. 9. Perform detailed routing using the layout tool. 10. Extract real timing delays from the detailed routed design. 11. Back-annotate the real extracted data to PrimeTime. 12. Post-layout static timing analysis using PrimeTime. 13. Functional gate-level simulation of the design with post-layout timing (if desired). 14. Tape out after LVS and DRC verification.